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Si1141/42/43
Table 9. Resource Summary for Hardware Pins
Pin Name
LED1
LED2
LED3
INT
LED Current Drive
LED1_I in PSLED12[3:0]
LED2_I in PSLED12[7:4]
LED3_I in PSLED3[3:0]
Output Drive Disable
HW_KEY[7:0]
HW_KEY[7:0]
INT_OE in INT_CFG[0]
Analog Voltage Input
Enable
ANA_IN_KEY[31:0]
ANA_IN_KEY[31:0]
ANA_IN_KEY[31:0]
The interrupts of the Si1141/42/43 are controlled through the INT_CFG, IRQ_ENABLE, IRQ_MODE1,
IRQ_MODE2 and IRQ_STATUS registers.
The INT hardware pin is enabled through the INT_OE bit in the INT_CFG register. The hardware essentially
performs an AND function between the IRQ_ENABLE register and IRQ_STATUS register. After this AND function,
if any bits are set, the INT pin is asserted. The INT_MODE bit in the INT_CFG register is conceptually a method of
determining how the INT pin is deasserted. When INT_MODE = 0, the host is responsible for clearing the interrupt
by writing to the IRQ_STATUS register. When the specific bits of the IRQ_STATUS register is written with '1', that
specific IRQ_STATUS bit is cleared.
Typically, the host software is expected to read the IRQ_STATUS register, stores a local copy, and then writes the
same value back to the IRQ_STATUS to clear the interrupt source. Unless specifically stated, INT_MODE should
be zero for normal interrupt handling operation. In summary, the INT_CFG register is normally written with '1'.
The IRQ_MODE1, IRQ_MODE2 and IRQ_ENABLE registers work together to define how the internal sequencer
sets bits in the IRQ_STATUS register (and as a consequence, asserting the INT pin).
The PS1 interrupts are described in Table 10. The PS2 interrupts are described in Table 11. The PS3 interrupts are
described in Table 12. The ALS interrupts are described in Table 13, and the Command Interface interrupts are
described in Table 14.
24
Rev. 1.3
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